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| PRELIMINARY ISD5100 SERIES SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY -1- Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 1. GENERAL DESCRIPTION The ISD5100 ChipCorder Series provide high quality, fully integrated, single-chip Record/Playback solutions for 1- to 16-minute messaging applications that are ideal for use in cellular phones, automotive communications, GPS/navigation systems and other portable products. The ISD5100 Series products are an enhancement of the ISD5000 architecture, providing: 1) the I2C serial port address, control and duration selection are accomplished through an I2C interface to minimize pin count (ONLY two control lines required); 2) the capability of storing digital data, in addition to analog data. This feature allows customers to store phone numbers, system configuration parameters and message address locations for message management capability; 3) Various internal circuit blocks can be individually powered-up or -down for power saving. The ISD5100 Series include: * * * * ISD5116 from 8 to 16 minutes ISD5108 from 4 to 8 minutes ISD5104 from 2 to 4 minutes ISD5102 from 1 to 2 minutes Analog functions and audio gating have also been integrated into the ISD5100 Series products to allow easy interface with integrated digital cellular chip sets on the market. Audio paths have been designed to enable full duplex conversation record, voice memo, answering machine (including outgoing message playback) and call screening features. This product enables playback of messages while the phone is in standby, AND both simplex and duplex playback of messages while on a phone call. Additional voice storage features for digital cellular phones include: 1) a personalized outgoing message can be sent to the person by getting caller-ID information from the host chipset, 2) a private call announce while on call can be heard from the host by giving caller-ID on call waiting information from the host chipset. Logic Interface Options of 2.0V and 3.0V are supported by the ISD5100 Series to accommodate portable communication products (2.0- and 3.0-volt required). Like other ChipCorder(R) products, the ISD5100 Series integrate the sampling clock, anti-aliasing and smoothing filters, and the multi-level storage array on a single-chip. For enhanced voice features, the ISD5100 Series eliminate external circuitry by integrating automatic gain control (AGC), a power amplifier/speaker driver, volume control, summing amplifiers, analog switches, and a car kit interface. Input level adjustable amplifiers are also included, providing a flexible interface for multiple applications. Recordings are stored into on-chip nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is made possible through Winbond's patented multilevel storage technology. Voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality on voice and music reproduction. -2- ISD5100 - SERIES 2. FEATURES Fully-Integrated Solution * * * Single-chip voice record/playback solution Dual storage of digital and analog data Durations 8 to 16-minute (ISD5116) 4 to 8-minute (ISD5108) 2 to 4-minute (ISD5104) 1 to 2-minute (ISD5102) +2.7 to +3.3V (VCC) Supply Voltage Supports 2.0V and 3.0V interface logic Operating Current: ICC Play = 15 mA (typical) ICC Rec = 30 mA (typical) ICC Feedthrough = 12 mA (typical) Standby Current: ISB = 1A (typical) Most stages can be individually powered down to minimize power consumption One or two-way conversation record One or two-way message playback Voice memo record and playback Private call screening In-terminal answering machine Personalized outgoing message Private call announce while on call Up to 4 Mb available (ISD5116) Up to 2 Mb available (ISD5108) Up to 1 Mb available (ISD5104) Up to 512Kb available (ISD5102) Storage of phone numbers, system configuration parameters and message address table in cellular application No compression algorithm development required User-controllable sampling rates Programmable analog interface Standard & Fast mode I2C serial interface (100kHz - 400 kHz) Fully addressable for multiple messages High quality voice and music reproduction Winbond's standard 100-year message retention (typical) 100K record cycles (typical) for analog data 10K record cycles (typical) for digital data Available in die form, TSOP and SOIC and PDIP (ISD5116 Only) Temperature: Commercial - Packaged (0 to +70C) & die (0 to +50C); Industrial (-40 to +85C) Low Power Consumption * * * * * * * * * * * * * * * * * Enhanced Voice Features Digital Memory Features Easy-to-use and Control * * * * * * * * * * * High Quality Solution Options -3- Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 3. BLOCK DIAGRAM ISD5100-Series Block Diagram 6dB FTHRU ANA OUT MUX INP FILTO INP SUM1 MUX SUM1 Summing AMP SUM1 ARRAY SUM1 MICROPHONE Input Source MUX MIC+ MIC AGCCAP 1.0 / 1.4 / 2.0 / 2.8 MIC IN AGC (AGPD) AUX IN 1 2 Low Pass Filter 1 FILTO ANA IN 2 (S1M0 ) S1M1 FILTO ANA IN ARRAY SUM2 Summing AMP ANA OUT AMP (AOPD) 1 ANA OUT+ ANA OUT- VOL SUM2 Filter MUX 1 (FLS0) (FLPD) ( S2M0 ) S2M1 AUX IN AUX IN AMP (INS0) (AXPD) 1 1 () AOS0 AOS1 AOS2 FILTO AUX OUT AMP 3 SUM1 MUX 2 Internal Clock SUM2 (ANALOG) 2 ( AXG0) AXG1 ( S1S0 ) S1S1 (FLD0 ) FLD1 ARRAY INPUT MUX Multilevel/Digital Storage Array Array I/OMux 64-bit/samp. 64-bit/samp. ARRAY OUT (DIGITAL) 2 AUX OUT SPEAKER SP+ SP- Output MUX XCLK 0.625/0.883/1.25/1.76 SUM2 VOL ANA IN CTRL (DIGITAL) ARRAY OUT (ANALOG) ARRAY OUTPUT MUX ANA IN ANA IN AMP (AIPD) 1 Spkr. AMP SUM1 INP ANA IN SUM2 Volume Control 1 ( AIG0 ) AIG1 Power Conditioning 2 (VLPD ) 3 () VOL0 VOL1 VOL2 ( OPS0 OPS1 2 ) (OPA0 ) OPA1 2 Vol MUX 2 ( VLS0 ) VLS1 Device Control VCCA VSSA VSSA VSSD VSSD VCCD VCCD SCL SDA INT RAC A0 A1 -4- ISD5100 - SERIES 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION...................................................................................................................2 2. FEATURES ..........................................................................................................................................3 3. BLOCK DIAGRAM................................................................................................................................4 4. TABLE OF CONTENTS .......................................................................................................................5 5. PIN CONFIGURATION ........................................................................................................................7 6. PIN DESCRIPTION ..............................................................................................................................8 7. FUNCTIONAL DESCRIPTION.............................................................................................................9 7.1. Overview ........................................................................................................................................9 7.1.1 Speech/Voice Quality...............................................................................................................9 7.1.2. Duration...................................................................................................................................9 7.1.3. Flash Technology....................................................................................................................9 7.1.4. Microcontroller Interface..........................................................................................................9 7.1.5. Programming.........................................................................................................................10 7.2. Functional Details ........................................................................................................................10 7.2.1. Internal Registers ..................................................................................................................11 7.2.2. Memory Architecture .............................................................................................................11 7.3. Operational Modes Description ...................................................................................................12 7.3.1. I2C Interface ..........................................................................................................................12 7.3.2. I2C Control Registers ............................................................................................................16 7.3.3. Opcode Summary .................................................................................................................17 7.3.4. Data Bytes.............................................................................................................................19 7.3.5. Configuration Resiter Bytes ..................................................................................................20 7.3.6. Power-up Sequence..............................................................................................................21 7.3.7. Feed Through Mode..............................................................................................................22 7.3.8. Call Record............................................................................................................................24 7.3.9. Memo Record........................................................................................................................25 7.3.10. Memo and Call Playback ....................................................................................................26 7.3.11. Message Cueing .................................................................................................................27 7.4. Analog Mode................................................................................................................................28 7.4.1. Aux In and Ana In Description...............................................................................................28 7.4.2. ISD5100 Series Analog Structure (left half) Description.......................................................29 7.4.3. ISD5100 Series Aanalog Structure (right half) Description ..................................................30 7.4.4. Volume Control Description ..................................................................................................31 7.4.5. Speaker and Aux Out Description.........................................................................................32 -5- Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.4.6. Ana Out Description ..............................................................................................................33 7.4.7. Analog Inputs ........................................................................................................................33 7.5. Digital Mode .................................................................................................................................36 7.5.1. Erasing Digital Data ..............................................................................................................36 7.5.2. Writing Digital Data ...............................................................................................................36 7.5.3. Reading Digital Data .............................................................................................................37 7.5.4. Example Command Sequences ...........................................................................................37 7.6. Pin Details....................................................................................................................................48 7.6.1. Digital I/O Pins.......................................................................................................................48 7.6.2. Analog I/O Pins .....................................................................................................................50 7.6.3. Power and Ground Pins ........................................................................................................54 7.6.4. PCB Layout Examples ..........................................................................................................55 8.1. I2C Timing Diagram......................................................................................................................56 8.2. Playback and Stop Cycle.............................................................................................................58 8.3. Example of Power Up Command (first 12 bits) ...........................................................................59 9. ABSOLUTE MAXIMUM RATINGS.....................................................................................................60 10. ELECTRICAL CHARACTERISTICS ................................................................................................62 10.1. General Parameters ..................................................................................................................62 10.2. Timing Parameters ....................................................................................................................63 10.3. Analog Parameters ....................................................................................................................65 10.4. Characteristics of The I2C Serial Interface ................................................................................69 10.5. I2C Protocol................................................................................................................................72 11. TYPICAL APPLICATION CIRCUIT ..................................................................................................74 12. PACKAGE SPECIFICATION ...........................................................................................................75 12.1. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 .................................75 12.2. 28-Lead 300-Mil Plastic Small Outline Integrated Circuit (SOIC)..............................................76 12.3. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ................................................................77 12.4 12.5 12.6 12.7 ISD5116 Die Information..........................................................................................................78 ISD5108 Die Information..........................................................................................................80 ISD5104 Die Information..........................................................................................................82 ISD5102 Die Information..........................................................................................................84 13. ORDERING INFORMATION............................................................................................................86 14. VERSION HISTORY ........................................................................................................................87 -6- ISD5100 - SERIES 5. PIN CONFIGURATION SCL A1 SDA A0 VSSD VSSD NC MIC+ VSSA MICANA OUT+ ANA OUTACAP SP- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ISD5116 ISD5108 ISD5104 ISD5102 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCCD VCCD XCLK INT RAC VSSA NC NC AUX OUT AUX IN ANA IN VCCA SP+ VSSA SCL A1 SDA A0 VSSD VSSD NC MIC+ VSSA MICANA OUT+ ANA OUTACAP SP- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ISD5116 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCCD VCCD XCLK INT RAC VSSA NC NC AUX OUT AUX IN ANA IN VCCA SP+ VSSA SOIC PDIP NC VSSA RAC INT XCLK VCCD VCCD SCL A1 SDA A0 VSSD VSSD NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 NC AUX OUT AUX IN ANA IN VCCA SP+ VSSA SPACAP ANA OUTANA OUT+ MICMIC+ VSSA ISD5116 ISD5108 ISD5104 ISD5102 24 23 22 21 20 19 18 17 16 15 TSOP -7- Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 6. PIN DESCRIPTION Pin Name SCL A1 SDA A0 VSSD NC MIC+ VSSA MICANA OUT+ ANA OUTACAP SPSP+ VCCA SOIC/PDIP 1 2 3 4 5,6 7,21,22 8 9,15,23 10 11 12 13 14 16 17 TSOP 8 9 10 11 12,13 1,14,28 16 2,15,22 17 18 19 20 21 23 24 Functionality I2C Serial Clock Line: to clock the data into and out of the I2C interface. Input pin that supplies the LSB +1 bit for the I2C Slave Address. I2C Serial Data Line: Data is passed between devices on the bus over this line. Input pin that supplies the LSB for the I2C Slave Address. Digital Ground. No Connect. Differential Positive Input for the microphone amplifier. Analog Ground. Differential Negative Input for the microphone amplifier. Differential Positive Analog Output for ANA OUT. Differential Negative Analog Output for ANA OUT. AGC/AutoMute Capacitor: Required for the on-chip AGC amplifier during record and AutoMute function during playback. Differential Negative Speaker Output: When the speaker outputs are in use, the AUX OUT output is disabled. Differential Positive Speaker Output. Analog Supply Voltage: This pin supplies power to the analog sections of the device. It should be carefully bypassed to Analog Ground to insure correct device operation. Analog Input: one of the analog inputs with selectable gain. Auxiliary Input: one of the analog inputs with selectable gain. Auxiliary Output: one the analog outputs of the device. When this output is used, the SP+ and SP- outputs are disabled. Row Address Clock; an open drain output. The RAC pin goes LOW TRACL[1] before the end of each row of memory and returns HIGH at exactly the end of each row of memory. Interrupt Output; an open drain output that indicates that a set EOM bit has been found during Playback or that the chip is in an Overflow (OVF) condition. This pin remains LOW until a Read Status command is executed. This pin allows the internal clock of the device to be driven externally for enhanced timing precision. This pin is grounded for most applications. Digital Supply Voltage. These pins supply power to the digital sections of the device. They must be carefully bypassed to Digital Ground to insure correct device operation. ANA IN AUX IN AUX OUT RAC 18 19 20 24 25 26 27 3 INT 25 4 XCLK VCCD 26 27,28 5 6,7 [1] See the Parameters section -8- ISD5100 - SERIES 7. FUNCTIONAL DESCRIPTION 7.1. OVERVIEW 7.1.1 Speech/Voice Quality The ISD5100 ChipCorder Series can be configured via software to operate at 4.0, 5.3, 6.4 or 8.0 kHz sampling frequency to select appropriate voice quality. Increasing the duration decreases the sampling frequency and bandwidth, which affects audio quality. The table in the following section shows the relationship between sampling frequency, duration and filter pass band. 7.1.2. Duration To meet system requirements, the ISD5100 Series are single-chip solution, which provide 1 to 16 minutes of voice record and playback, depending upon the sample rates chosen. Sample Rate (kHz) 8.0 6.4 5.3 4.0 [1] Duration [1] ISD5116 8 min 44 sec 10 min 55 sec 13 min 6 sec 17 min 28 sec ISD5108 4 min 22 sec 5 min 27 sec 6 min 33 sec 8 min 44 sec ISD5104 2 min 11 sec 2 min 43 sec 3 min 17 sec 4 min 22 sec ISD5102 1 min 5 sec 1 min 21 sec 1 min 38 sec 2 min 11 sec Typical Filter Knee (kHz) 3.4 2.7 2.3 1.7 Minus any pages selected for digital storage 7.1.3. Flash Technology One of the benefits of Winbond's ChipCorder technology is the use of on-chip Flash memory, which provides zero-power message storage. The message is retained for up to 100 years (typically) without power. In addition, the device can be re-recorded over 10,000 times (typically) for the digital data and over 100,000 times (typically) for the analog messages. A new feature has been added that allows memory space in the ISD5100 Series to be allocated to either digital or analog storage when recorded. The fact that a section has been assigned digital or analog data is stored in the Message Address Table by the system microcontroller when the recording is made. 7.1.4. Microcontroller Interface The ISD5100 Series are controlled through an I2C 2-wire interface. This synchronous serial port allows commands, configurations, address data, and digital data to be loaded into the device, while allowing status, digital data and current address information to be read back from the device. In addition to the serial interface, two other status pins can feedback to the microcontroller for enhanced Publication Release Date: October, 2003 Revision 0.2 -9- ISD5100 - SERIES interface. These are the RAC timing pin and the INT pin for interrupts to the controller. Communications with all the internal registers of any operations are through the serial bus, as well as digital memory Read and Write operations. 7.1.5. Programming The ISD5100 Series are also ideal for playback-only applications, where single or multiple messages may be played back when desired. Playback is controlled through the I2C interface. Once the desired message configuration is created, duplicates can easily be generated via a third-party programmer. For more information on available application tools and programmers, please see the Winbond web site at www.winbond-usa.com 7.2. FUNCTIONAL DETAILS The ISD5100 Series are single chip solutions for analog and digital data storage. The array can be divided between analog and digital storage according to user's choice, when the device is configured. The below block diagram shows that the ISD5116 device can be easily designed into a telephone answering machine (TAD). Both Mic inputs transmit the voice input signal from the microphone to perform OGM recording, as well as to record the speech during phone conversation (simplex). When the TAD is activated, the voice of the other party from the phone line feeds into the AUX IN, and is recorded into the ISD5116 device. Then the new messge is usually indicated with blinking new message LED. Hence, during playback, the recorded message is sent out to speaker with volume control. Two I2C pins are used for all communications between the ChipCorder and the microcontroller for analog and/or digital storage, and the two outputs, INT and RAC are feedback to microcontroller for message management. DTMF Detect, Caller ID ANA OUT+ MIC+ MICSP+ SP- ISD5116 Microcontroller IC (INT, RAC) AUX IN 2 AUX OUT Speaker Display & Push buttons NV Memory DAA Phone Line For duplex recording, speech from Mic inputs and message from received path can be directly recorded into the array simultaneously, then playback afterwards. In addition, for speaker phone - 10 - ISD5100 - SERIES operation, voice from Mic inputs are fed to AUX OUT and transmitted to the phone line, while message from other party is input from the AUX IN, then fed through to the speaker for listening. The ISD5100 device has the flexibility for other applications, because the audio paths can be configured differently, with each circuit block being powered-up or -down individually, according to the applications requirement. 7.2.1. Internal Registers The ISD5100 Series have multiple internal registers that are used to store the address information and the configuration or set-up of the device. The two 16-bit configuration registers control the audio paths through the device, the sample frequency, the various gains and attenuations, power up and down of different sections, and the volume settings. These registers are discussed in detail in section 7.3.5. 7.2.2. Memory Architecture The ISD5100 Series memory array are arranged in various pages (or rows) of each 2048 bits as follows. The primary addressing for the pages are handled by 11 bits of address input in the analog mode. A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. The contents of a page are either analog or digital. This is determined by instruction (opcode) at the time the data is written. A record of where is analog and where is digital, is stored in a message address table (MAT) by the system microcontroller. The MAT is a table kept in the microcontroller memory that defines the status of each message "page". It can be stored back into the ISD5100 Series if the power fails or the system is turned off. Using this table allows efficient message management. Segments of messages can be stored wherever there is available space in the memory array. [This is explained in detail for the ISD5008 in Applications Note #9 and will be similarly described in a later Note for the ISD5100-Series.] Products ISD5116 ISD5108 ISD5104 ISD5102 Pages (Rows) 2048 1024 512 256 Bits/Page 2048 2048 2048 2048 Memory Size 4,194,304 bits 2,097,152 bits 1,048,576 bits 524,288 bits When a page is used for analog storage, the same 32 blocks are present but there are 8 EOM (Endof-Message) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus, when recording, the analog recording will stop at any one of eight positions. At 8 kHz sampling frequency, this results in a resolution of 32 msec when ENDING an analog recording. Beginning an analog recording is limited to the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when the Stop command is given, but continues until the 32 millisecond block is filled. Then a bit is placed in the EOM memory to develop the interrupt that signals a message is finished playing in the Playback mode. - 11 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES Digital data is sent and received serially over the I2C interface. The data is serial-to-parallel converted and stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it becomes the register that is parallel written into the array. The prior write register becomes the new serial input register. A mechanism is built-in to ensure there is always a register available for storing new data. Storing data in the memory is accomplished by accepting data one byte at a time and issuing an acknowledge. If data is coming in faster than it can be written, the chip issues an acknowledge to the host microcontroller, but holds SCL LOW until it is ready to accept more data. (See section 7.5.2 for details). The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the array and serially sent to the I2C interface. (See section 7.5.3 for details). 7.3. OPERATIONAL MODES DESCRIPTION 7.3.1. I2C Interface To use more than four ISD5100 Series devices in an application requires some external switching of the I2C interface. I2C interface Important note: The rest of this data sheet will assume that the reader is familiar with the I2C serial interface. Additional information on I2C may be found in section 10 on page 72 of this document. If you are not familiar with this serial protocol, please read this section to familiarize yourself with it. A large amount of additional information on I2C can also be found on the Philips web page at http://www.philips.com/. I2C Slave Address The ISD5100 Series have 7-bit slave address of <100 00xy> where x and y are equal to the state, respectively, of the external address pins A1 and A0. Because all data bytes are required to be 8 bits, the LSB of the address byte is the Read/Write selection bit that tells the slave whether to transmit or receive data. Therefore, there are 8 possible slave addresses for the ISD5100-Series. These are: - 12 - ISD5100 - SERIES Pinout Table A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Slave Address <100 0000> <100 0001> <100 0010> <100 0011> <100 0000> <100 0001> <100 0010> <100 0011> R/W Bit HEX Value 80 82 84 86 81 83 85 87 0 0 0 0 1 1 1 1 ISD5100 Series I2C Operation Definitions There are many control functions used to operate the ISD5100-Series. Among them are: 7.3.1.1. Read Status Command: The Read Status command is a read request from the Host processor to the ISD5100 Series without delivering a Command Byte. The Host supplies all the clocks (SCL). In each case, the entity sending the data drives the data line (SDA). The Read Status Command is executed by the following I2C sequence. 1. Host executes I2C START 2. Send Slave Address with R/W bit = "1" (Read) 81h 3. Slave (ISD5100-Series) responds back to Host an Acknowledge (ACK) followed by 8-bit Status word 4. Host sends an Acknowledge (ACK) to Slave 5. Wait for SCL to go HIGH 6. Slave responds with Upper Address byte of internal address register 7. Host sends an ACK to Slave 8. Wait for SCL to go HIGH 9. Slave responds with Lower Address byte of internal address register (A[4:0] will always return set to 0.) 10. Host sends a NO ACK to Slave, then executes I2C STOP - 13 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES Note that the processor could have sent an I2C STOP after the Status Word data transfer and aborted the transfer of the Address bytes. A graphical representation of this operation is found below. See the caption box above for more explanation. Conventions used in I2C Data Transfer Diagrams S P DATA R W A N = START Condition = STOP Condition = 8-bit data transfer = "1" in the R/W bit = "0" in the R/W bit = ACK (Acknowledge) = No ACK = 7-bit Slave SLAVE ADDRESS Address The Box color indicates the direction of data flow = Host to Slave (Gray) = Slave to Host (White) S SLAVE ADDRESS R A DATA A DATA A DATA N P Status High Addr. Low Addr. - 14 - ISD5100 - SERIES 7.3.1.2. Load Command Byte Register (Single Byte Load): A single byte may be written to the Command Byte Register in order to power up the device, start or stop Analog Record (if no address information is needed), or do a Message Cueing function. The Command Byte Register is loaded as follows: S 1. Host executes I2C START 2. Send Slave Address with R/W bit = "0" (Write) [80h] 3. Slave responds back with an ACK. 4. Wait for SCL to go HIGH 5. Host sends a command byte to Slave 6. Slave responds with an ACK 7. Wait for SCL to go HIGH 8. Host executes I2C STOP Command Byte SLAVE ADDRESS W A DATA A P 7.3.1.3. Load Command Byte Register (Address Load) For the normal addressed mode the Registers are loaded as follows: 1. Host executes I2C START 2. Send Slave Address with R/W bit = "0" (Write) 3. Slave responds back with an ACK. 4. Wait for SCL to go HIGH 5. Host sends a byte to Slave - (Command Byte) 6. Slave responds with an ACK 7. Wait for SCL to go HIGH 8. Host sends a byte to Slave - (High Address Byte) 9. Slave responds with an ACK 10. Wait for SCL to go HIGH 11. Host sends a byte to Slave - (Low Address Byte) 12. Slave responds with an ACK 13. Wait for SCL to go HIGH 14. Host executes I2C STOP S SLAVE ADDRESS W A DATA A DATA A DATA A P Command High Addr. Low Addr. - 15 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.3.2. I2C Control Registers The ISD5100 Series are controlled by loading commands to, or, reading from, the internal command, configuration and address registers. The Command byte sent is used to start and stop recording, write or read digital data and perform other functions necessary for the operation of the device. Command Byte Control of the ISD5100 Series are implemented through an 8-bit command byte, sent after the 7-bit device address and the 1-bit Read/Write selection bit. The 8 bits are: Global power up bit DAB bit: determines whether device is performing an analog or digital function 3 function bits: these determine which function the device is to perform in conjunction with the DAB bit. 3 register address bits: these determine if and when data is to be loaded to a register Power Up Bit C7 PU C6 DAB C5 FN2 C4 FN1 C3 FN0 C2 RG2 C1 RG1 Register Bits C0 RG0 Function Bits Function Bits The command byte function bits are detailed in the table to the right. C6, the DAB bit, determines whether the device is performing an analog or digital function. The other bits are decoded to produce the individual commands. Not all decode combinations are currently used, and are reserved for future use. Out of 16 possible codes, the ISD5100 Series uses 7 for normal operation. The other 9 are undefined Function Bits C6 DAB 0 0 0 0 1 1 1 C5 FN2 0 1 0 1 1 0 0 C4 FN1 0 0 1 1 0 0 1 C3 FN0 0 1 0 1 0 1 0 Function STOP (or do nothing) Analog Play Analog Record Analog MC Digital Read Digital Write Erase (row) - 16 - ISD5100 - SERIES Register Bits The register load may be used to modify a command sequence (such as load an address) or used with the null command sequence to load a configuration or test register. Not all registers are accessible to the user. [RG2 is always 0 as the four additional combinations are undefined.] RG2 C2 0 0 0 0 RG1 C1 0 0 1 1 RG0 C0 0 1 0 1 No action Reserved Load CFG0 Load CFG1 Function 7.3.3. Opcode Summary OpCode Command Description The following commands are used to access the chip through the I2C interface. Play: analog play command Record: analog record command Message Cue: analog message cue command Read: digital read command Write: digital write command Erase: digital page and block erase command Power up: global power up/down bit. (C7) Load CFG0: load configuration register 0 Load CFG1: load configuration register 1 Read STATUS: Read the interrupt status and address register, including a hardwired device ID - 17 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES OPCODE COMMAND BYTE TABLE Pwr OPCODE COMMAND BIT NUMBER HEX CMD PU C7 DAB C6 Function Bits FN2 C5 FN1 C4 FN0 C3 Register Bits RG2 C2 RG1 C1 RG0 C0 POWER UP POWER DOWN STOP (DO NOTHING) STAY ON STOP (DO NOTHING) STAY OFF LOAD CFG0 LOAD CFG1 RECORD ANALOG RECORD ANALOG @ ADDR PLAY ANALOG PLAY ANALOG @ ADDR MSG CUE ANALOG MSG CUE ANALOG @ ADDR 80 00 80 00 82 83 90 91 A8 A9 B8 B9 C0 40 D0 D1 C8 C9 E0 E1 N/A 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 N/A 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 N/A 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 N/A 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 N/A 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 N/A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N/A 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N/A 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 N/A ENTER DIGITAL MODE EXIT DIGITAL MODE DIGITAL ERASE PAGE DIGITAL ERASE PAGE @ ADDR DIGITAL WRITE DIGITAL WRITE @ ADDR DIGITAL READ DIGITAL READ @ ADDR READ STATUS1 1. See section 7.2 on page 12 for details. - 18 - ISD5100 - SERIES 7.3.4. Data Bytes In the I C write mode, the device can accept data sent after the command byte. If a register load option is selected, the next two bytes are loaded into the selected register. The format of the data is MSB first, the I2C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first, the byte is acknowledged, and DATA<7:0> is sent next. The address register consists of two bytes. The format of the address is as follows: ADDRESS<15:0> = PAGE_ADDRESS<10:0>, BLOCK_ADDRESS<4:0> 2 Note: if an analog function is selected, the block address bits must be set to 00000. Digital Read and Write are block addressable. When the device is polled with the Read Status command, it will return three bytes of data. The first byte is the status byte, the next the upper address byte and the last the lower address byte. The status register is one byte long and its bit function is: STATUS<7:0> = EOM, OVF, READY, PD, PRB, DEVICE_ID<2:0> Lower address byte will always return the block address bits as zero, either in digital or analog mode. The functions of the bits are: EOM OVF READY PD PRB DEVICE_ID BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 0, 1, 2 Indicates whether an EOM interrupt has occurred. Indicates whether an overflow interrupt has occurred. Indicates the internal status of the device - if READY is LOW no new commands should be sent to device, i.e. Not Ready. Device is powered down if PD is HIGH. Play/Record mode indicator. HIGH=Play/LOW=Record. An internal device ID. ISD5116 = 001; ISD5104 = 100 and ISD5102 = 101. ISD5108 = 010; It is recommended that you read the status register after a Write or Record operation to ensure that the device is ready to accept new commands. Depending upon the design and the number of pins available on the controller, the polling overhead can be reduced. If INT and RAC are tied to the microcontroller, it does not have to poll as frequently to determine the status of the ISD5100-SERIES. - 19 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.3.5. Configuration Resiter Bytes The configuration register bytes are defined, in detail, in the drawings of section 7.4 on page 29. The drawings display how each bit enables or disables a function of the audio paths in the ISD5100Series. The tables below give a general illustration of the bits. There are two configuration registers, CFG0 and CFG1, so there are four 8-bit bytes to be loaded during the set-up of the device. Configuration Register 0 (CFG0) AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0 Volume Control Power Down SPKR & AUX OUT Control (2 bits) OUTPUT MUX Select (2 bits) ANA OUT Power Down AUXOUT MUX Select (3 bits) INPUT SOURCE MUX Select (1 bit) AUX IN Power Down AUX IN AMP Gain SET (2 bits) ANA IN Power Down ANA IN AMP Gain SET (2 bits) - 20 - ISD5100 - SERIES Configuration Register 1 (CFG1) VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0 AGC AMP Power Down Filter Power Down SAMPLE RATE (& Filter) Set up (2 bits) FILTER MUX Select SUM 2 SUMMING AMP Control (2 bits) SUM 1 SUMMING AMP Control (2 bits) SUM 1 MUX Select (2 bits) VOLUME CONTROL (3 bits) VOLUME CONT. MUX Select (2 bits) 7.3.6. Power-up Sequence This sequence prepares the ISD5100 Series for an operation to follow, waiting the Tpud time before sending the next command sequence. 1. 2. 3. 4. 5. 6. 7. 8. Send I2C POWER UP Send one byte 10000000 {Slave Address, R/W = 0} 80h Slave ACK Wait for SCL High Send one byte 10000000 {Command Byte = Power Up} 80h Slave ACK Wait for SCL High Send I2C STOP Playback Mode The command sequence for an analog Playback operation can be handled several ways. The most straightforward approach would be to incorporate a single four byte exchange, which consists of the Slave Address (80h), the Command Byte (A9h) for Play Analog @ Address, and the two address bytes. - 21 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES Record Mode The command sequence for an Analog Record would be a four byte sequence consisting of the Slave Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes. See "Load Command Byte Register (Address Load)" in section 7.3.2 on page 17. 7.3.7. Feed Through Mode The previous examples were dependent upon the device already being powered up and the various paths being set through the device for the desired operation. To set up the device for the various paths requires loading the two 16-bit Configuration Registers with the correct data. For example, in the Feed Through Mode the device only needs to be powered up and a few paths selected. This mode enables the ISD5100 Series to connect to a cellular or cordless base band phone chip set without affecting the audio source or destination. There are two paths involved, the transmit path and the receive path. The transmit path connects the Winbond chip's microphone source through to the microphone input on the base band chip set. The receive path connects the base band chip set's speaker output through to the speaker driver on the Winbond chip. This allows the Winbond chip to substitute for those functions and incidentally gain access to the audio to and from the base band chip set. To set up the environment described above, a series of commands need to be sent to the ISD5100Series. First, the chip needs to be powered up as described in this section. Then the Configuration Registers must be filled with the specific data to connect the paths desired. In the case of the Feed Through Mode, most of the chip can remain powered down. The following figure illustrates the affected paths. FTHRU 6 dB INP Microphone Mic+ MicVOL FILTO SUM1 SUM2 3 ANA OUT MUX Chip Set ANA OUT+ ANA OUT- 1 [AOPD] [AOS2,AOS1,AOS0] Chip Set ANA IN ANA IN AMP 1 2 [APD] VOL ANA IN AMP FILTO SUM2 2 OUTPUT MUX Speaker SP+ SP2 [OPA1,OPA0] [AIG1,AIG0] [OPS1,OPS0] The figure above shows the part of the ISD5100 Series block diagram that is used in Feed Through Mode. The rest of the chip will be powered down to conserve power. The bold lines highlight the audio paths. Note that the Microphone to ANA OUT +/- path is differential. - 22 - ISD5100 - SERIES To select this mode, the following control bits must be configured in the ISD5100 Series configuration registers. To set up the transmit path: 1. Select the FTHRU path through the ANA OUT MUX--Bits AOS0, AOS1 and AOS2 control the state of the ANA OUT MUX. These are the D6, D7 and D8 bits respectively of Configuration Register 0 (CFG0) and they should all be ZERO to select the FTHRU path. 2. Power up the ANA OUT amplifier--Bit AOPD controls the power up state of ANA OUT. This is bit D5 of CFG0 and it should be a ZERO to power up the amplifier. To set up the receive path: 1. Set up the ANA IN amplifier for the correct gain--Bits AIG0 and AIG1 control the gain settings of this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin determines the setting of this gain stage. The ANA IN Amplifier Gain Settings table on page 36 will help determine this setting. In this example, we will assume that the peak signal never goes above 1 volt p-p single ended. That would enable us to use the 9 dB attenuation setting, or where D14 is ONE and D15 is ZERO. 2. Power up the ANA IN amplifier--Bit AIPD controls the power up state of ANA IN. This is bit D13 of CFG0 and should be a ZERO to power up the amplifier. 3. Select the ANA IN path through the OUTPUT MUX--Bits OPS0 and OPS1 control the state of the OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to the state where D3 is ONE and D4 is ZERO to select the ANA IN path. 4. Power up the Speaker Amplifier--Bits OPA0 and OPA1 control the state of the Speaker and AUX amplifiers. These are bits D1 and D2 respectively of CFG0. They should be set to the state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures it for its higher gain setting for use with a piezo speaker element and also powers down the AUX output stage. The status of the rest of the functions in the ISD5100 Series chip must be defined before the configuration registers settings are updated: 1. Power down the Volume Control Element--Bit VLPD controls the power up state of the Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this stage. 2. Power down the AUX IN amplifier--Bit AXPD controls the power up state of the AUX IN input amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage. 3. Power down the SUM1 and SUM2 Mixer amplifiers--Bits S1M0 and S1M1 control the SUM1 mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1 and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down these two amplifiers. 4. Power down the FILTER stage--Bit FLPD controls the power up state of the FILTER stage in the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage. 5. Power down the AGC amplifier--Bit AGPD controls the power up state of the AGC amplifier. This is bit D0 in CFG1 and should be set to a ONE to power down this stage. - 23 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 6. Don't Care bits--The following stages are not used in Feed Through Mode. Their bits may be set to either level. In this example, we will set all the following bits to a ZERO. (a). Bit INS0, bit D9 of CFG0 controls the Input Source Mux. (b). Bits AXG0 and AXG1 are bits D11 and D12 respectively in CFG0. They control the AUX IN amplifier gain setting. (c). Bits FLD0 and FLD1 are bits D2 and D3 respectively in CFG1. They control the sample rate and filter band pass setting. (d). Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX. (e). Bits S1S0 and S1S1 are bits D9 and D10 of CFG1. They control the SUM1 MUX. (f). Bits VOL0, VOL1 and VOL2 are bits D11, D12 and D13 of CFG1. They control the setting of the Volume Control. (g). Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control MUX. The end result of the above set up is CFG0=0100 0100 0000 1011 (hex 440B) and CFG1=0000 0001 1110 0011 (hex 01E3). Since both registers are being loaded, CFG0 is loaded, followed by the loading of CFG1. These two registers must be loaded in this order. The internal set up for both registers will take effect synchronously with the rising edge of SCL. 7.3.8. Call Record The call record mode adds the ability to record an incoming phone call. In most applications, the ISD5100 Series would first be set up for Feed Through Mode as described above. When the user wishes to record the incoming call, the setup of the chip is modified to add that ability. For the purpose of this explanation, we will use the 6.4 kHz sample rate during recording. The block diagram of the ISD5100 Series shows that the Multilevel Storage array is always driven from the SUM2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, THE FILTER MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed Through Mode has already powered up the ANA IN amp so we only need to power up and enable the path to the Multilevel Storage array from that point: 1. Select the ANA IN path through the SUM1 MUX--Bits S1S0 and S1S1 control the state of the SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set to the state where both D9 and D10 are ZERO to select the ANA IN path. 2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier--Bits S1M0 and S1M1 control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select the SUM1 MUX (only) path. 3. Select the SUM1 SUMMING amplifier path through the FILTER MUX--Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. - 24 - ISD5100 - SERIES 4. Power up the LOW PASS FILTER--Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 5. Select the 6.4 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO. 6. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier--Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. In this mode, the elements of the original PASS THROUGH mode do not change. The sections of the chip not required to add the record path remain powered down. In fact, CFG0 does not change and remains CFG0=0100 0100 0000 1011 (hex 440B). CFG1 changes to CFG1=0000 0000 1100 0101 (hex 00C5). Since CFG0 is not changed, it is only necessary to load CFG1. Note that if only CFG0 was changed, it would be necessary to load both registers. 7.3.9. Memo Record The Memo Record mode sets the chip up to record from the local microphone into the chip's Multilevel Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down and is not active in this mode. The path to be used is microphone input to AGC amplifier, then through the INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL STORAGE ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may be powered down. 1. Power up the AGC amplifier--Bit AGPD controls the power up state of the AGC amplifier. This is bit D0 of CFG1 and must be set to ZERO to power up this stage. 2. Select the AGC amplifier through the INPUT SOURCE MUX--Bit INS0 controls the state of the INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC amplifier. 3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier--Bits S1M0 and S1M1 control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT SOURCE MUX (only) path. 4. Select the SUM1 SUMMING amplifier path through the FILTER MUX--Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. - 25 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 5. Power up the LOW PASS FILTER--Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 6. Select the 5.3 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE. 7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier--Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. To set up the chip for Memo Record, the configuration registers are set up as follows: CFG0=0010 0100 0010 0001 (hex 2421). CFG1=0000 0001 0100 1000 (hex 0148). Only those portions necessary for this mode are powered up. 7.3.10. Memo and Call Playback This mode sets the chip up for local playback of messages recorded earlier. The playback path is from the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a piezo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be powered down. 1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX--Bit FLS0, the state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the MULTILEVEL STORAGE ARRAY. 2. Power up the LOW PASS FILTER--Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 3. Select the 8.0 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO. 4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier --Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. 5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX--Bits VLS0 and VLS1 control the state VOLUME MUX. These bits are bits D14 and D15, respectively of CFG1. They should be set to the state where D14 is ONE and D15 is ZERO to select the SUM2 SUMMING amplifier. - 26 - ISD5100 - SERIES 6. Power up the VOLUME CONTROL LEVEL--Bit VLPD controls the power-up state of the VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to power-up the VOLUME CONTROL. 7. Select a VOLUME CONTROL LEVEL--Bits VOL0, VOL1, and VOL2 control the state of the VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary count of 000 through 111 controls the amount of attenuation through that state. In most cases, the software will select an attenuation level according to the desires of the current users of the product. In this example, we will assume the user wants an attenuation of -12 dB. For that setting, D11 should be set to ONE, D12 should be set to ONE, and D13 should be set to a ZERO. 8. Select the VOLUME CONTROL path through the OUTPUT MUX--These are bits D3 and D4, respectively, of CFG0. They should be set to the state where D3 is ZERO and D4 is a ZERO to select the VOLUME CONTROL. 9. Power up the SPEAKER amplifier and select the HIGH GAIN mode--Bits OPA0 and OPA1 control the state of the speaker (SP+ and SP-) and AUX OUT outputs. These are bits D1 and D2 of CFG0. They must be set to the state where D1 is ONE and D2 is ZERO to power-up the speaker outputs in the HIGH GAIN mode and to power-down the AUX OUT. To set up the chip for Memo or Call Playback, the configuration registers are set up as follows: CFG0=0010 0100 0010 0010 (hex 2422). CFG1=0101 1001 1101 0001 (hex 59D1). Only those portions necessary for this mode are powered up. 7.3.11. Message Cueing Message cueing allows the user to skip through analog messages without knowing the actual physical location of the message. This operation is used during playback. In this mode, the messages are skipped 512 times faster than in normal playback mode. It will stop when an EOM marker is reached. Then, the internal address counter will be pointing to the next message. - 27 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.4. ANALOG MODE 7.4.1. Aux In and Ana In Description The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone "car kit." This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the AUX IN Amplifier Gain Settings table on page 37. Additional gain is available in 3 dB steps (controlled by the I2C serial interface) up to 9 dB. Internal to the device Rb CCOUP=0.1 F AUX IN Input AUX IN Input Amplifier Ra NOTE: fCUTOFF= 1 2RaCCOUP The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the serial bus) to the speaker output, the array input or to various other paths. This pin is designed to accept a nominal 1.11 Vp-p when at its minimum gain (6 dB) setting. See the ANA IN Amplifier Gain Settings table on page 37. There is additional gain available in 3 dB steps controlled from the I2C interface, if required, up to 15 dB. Internal to the device Rb CCOUP=0.1 F ANA IN Input ANA IN Input Amplifier Ra NOTE: fCUTOFF= 1 2RaCCOUP - 28 - ISD5100 - SERIES 7.4.2. ISD5100 Series Analog Structure (left half) Description INP INPUT SOURCE MUX AGC AMP SUM1 SUMMING AMP 2 (S1M1,S1M0) SUM1 AUX IN AMP (INS0) SUM1 MUX FILTO ANA IN AMP ARRAY INSO 0 1 Source AGC AMP AUX IN AMP S1S1 S1M1 0 0 1 1 S1S0 0 1 0 1 S1M0 0 1 0 1 SOURCE BOTH SUM1 MUX ONLY INP Only Power Down SOURCE ANA IN ARRAY FILTO N/C 2 (S1S1,S1S0) 0 0 1 1 15 AIG1 15 VLS1 14 AIG0 14 VLS0 13 AIPD 13 12 11 10 AXPD 10 S1S1 9 INS0 9 S1 S0 8 AOS2 8 S1M1 7 6 5 4 OPS1 4 FLS0 3 OPS0 3 FLD1 2 OPA1 2 FLD0 1 0 AX G1 AXG0 12 11 V OL0 AOS1 AOS0 AOPD 7 6 5 OPA0 V LPD 1 FLPD 0 AGPD C FG0 C FG1 V OL2 VOL1 S1M0 S2 M1 S2M0 - 29 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.4.3. ISD5100 Series Aanalog Structure (right half) Description FILTER FILTER FILTO FILTO MUX MUX SUM1 LOW PASS FILTER ARRAY FLS0 0 1 SOURCE SUM1 ARRAY SUM2 SUMMING AMP 2 (S2M1,S2M0) SUM2 1 1 (FLS0) (FLPD) S2M1 0 0 1 1 S2M0 0 1 0 1 SOURCE BOTH ANA IN ONLY FILTO ONLY Power Down FLPD 0 1 CONDITION Power Up Power Down ANA IN AMP MULTILEVEL STORAGE ARRAY XCLK FLD1 0 0 1 1 FLD0 0 1 0 1 SAMPLE RATE 8 KHz 6.4 KHz 5.3 KHz 4.0 KHz FILTER BANDWIDTH 3.6 KHz 2.9 KHz 2.4 KHz 1.8 KHz INTERNAL CLOCK 2 (FLD1,FLD0) ARRAY 15 VLS1 14 VLS0 13 VOL2 12 11 10 S1S1 9 S1S0 8 7 6 5 S2M0 4 FLS0 3 FLD1 2 FLD0 1 0 VOL1 VOL0 S1M1 S1M0 S2M1 FLP D AGPD CFG1 - 30 - ISD5100 - SERIES 7.4.4. Volume Control Description ANA IN AMP VOL MUX SUM2 SUM1 VOLUME CONTROL INP VLPD CONDITION Power Up Power Down VOL 2 (VLS1,VLS0) 3 1 (VLPD) ( VOL2,VOL1,VOL0) 0 1 VLS1 VLS0 SOURCE 0 0 1 1 0 1 0 1 ANA IN AMP SUM2 SUM1 INP VOL2 0 0 0 0 1 1 1 1 VOL1 0 0 1 1 0 0 1 1 VOL 0 0 1 0 1 0 1 0 1 ATTENUATION 0 dB 4 dB 8 dB 12 dB 16 dB 20 dB 24 dB 28 dB AIG1 15 V LS1 AIG0 AIP D 14 V LS0 13 VOL2 AXG1 AXG0 AX PD 12 11 10 S1 S1 INS0 9 S1S0 AOS2 8 S1M1 AOS1 AOS0 7 6 AOPD OPS1 OPS0 5 S2M0 4 FLS0 3 FLD1 OPA1 OPA0 VLPD 2 FLD0 1 FLPD 0 AGPD CFG0 CFG1 VOL1 VOL0 S1 M0 S2M1 - 31 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.4.5. Speaker and Aux Out Description OUTPUT MUX VOL Car Kit AUX OUT (1 Vp-p Max) ANA IN AMP SP+ FILTO SP- 2 ( OPA1, OPA0) 2 ( OPS1,OPS0) OPA1 0 OPS1 0 0 1 1 OPS0 0 1 0 1 SOURCE VOL ANA IN FILTO SUM2 0 1 1 OPA0 SPKR DRIVE 0 1 0 1 Power Down 3.6 VP-P @ 150 23.5 mWatt @ 8 Power Down AUX OUT Power Down Power Down Power Down 1 VP-P Max @ 5 K Sp eaker SUM2 15 AIG1 14 13 12 11 10 9 8 AOS2 7 6 5 4 3 2 1 0 AIG0 AIP D AXG1 AXG0 AXPD INS0 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0 - 32 - ISD5100 - SERIES 7.4.6. Ana Out Description *FTHRU *INP *VOL ANA OUT + *FILT O ANA OUT - *SUM1 *SUM2 1 (AOPD) 3 (AOS2,AOS1,AOS0) AOS2 0 0 0 AOS1 0 0 1 1 0 0 1 1 AOS0 0 1 0 1 0 1 0 1 SOURCE FTHRU INP VOL FILTO SUM1 SUM2 N/C N/C AOPD 0 1 CONDITION Power Up Power Down (1 Vp-p max. from AUX IN or ARRAY) (69 4 mV p-p max. from mi crophone input) Chip Set *DIFFERENTIAL PATH 0 1 1 1 1 15 AI G1 14 AI G0 13 AIPD 12 11 10 9 I NS0 8 7 6 5 4 OPS1 3 2 1 0 AXG1 AXG0 AXPD AOS2 AOS1 AOS0 AOPD OPS0 OPA1 OPA0 VLPD CFG0 7.4.7. Analog Inputs Microphone Inputs The microphone inputs transfer the voice signal to the on-chip AGC preamplifier or directly to the ANA OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6 dB so a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the ANA OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage array from a typical electric microphone output of 2 to 20 mV p-p. The input impedance is typically 10k. The ACAP pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It should have a 4.7 F capacitor connected to ground. It cannot be left floating. This is because the capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the amount of noise present in the output during quiet pauses. Tying this pin to ground gives maximum gain; to VCCA gives minimum gain for the AGC amplifier but will cancel the AutoMute function. - 33 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES * 6 dB FTHRU AGPD CONDITION Power Up Power Down MIC+ AGC M- IC 1 ( AGPD) To AutoMute ACAP (Pl ayback Only) * Di ffe re nti al Path 15 VLS1 14 VLS0 13 VOL2 12 VOL1 11 V OL0 10 S1S1 9 S1S0 8 S1M1 7 6 5 4 FLS0 3 FLD1 2 FLD0 1 0 AGC MIC IN 1 0 AGPD S1M0 S2M1 S2M0 FLPD CFG1 ANA IN (Analog Input) The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I2C interface) to the speaker output, the array input or to various other paths. This pin is designed to accept a nominal 1.11 V p-p when at its minimum gain (6 dB) setting. There is additional gain available, if required, in 3 dB steps, up to 15 dB. The gain settings are controlled from the I2C interface. Internal to the device Rb CCOUP = 0.1 F ANA IN Input Ra ANA IN Input Amplifier Gain Setting 00 01 10 11 Resistor Ratio (Rb/Ra) 63.9 / 102 77.9 / 88.1 92.3 / 73.8 106 / 60 Gain 0.625 0.883 1.250 1.767 Gain2 (dB) -4.1 -1.1 1.9 4.9 Note: Ra & Rb are in k NOTE: fCUTTOFF 1 2xRaCCOUP ANA IN Amplifier Gain Settings Setting(1) 6 dB 9 dB 12 dB 15 dB 0TLP Input VP-P(3) 1.110 0.785 0.555 0.393 CFG0 AIG1 0 0 1 1 AIG0 0 1 0 1 Gain(2) 0.625 0.883 1.250 1.767 Array In/Out VP-P 0.694 0.694 0.694 0.694 Speaker Out VP-P(4) 2.22 2.22 2.22 2.22 - 34 - ISD5100 - SERIES 1. Gain from ANA IN to SP+/2. Gain from ANA IN to ARRAY IN 3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping 4. Speaker Out gain set to 1.6 (High). (Differential) AUX IN (Auxiliary Input) The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone "car kit." This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the following table. Additional gain is available in 3 dB steps (controlled by the I2C interface) up to 9 dB. AUX IN Input Modes Internal to the device Rb CCOUP = 0.1 F AUX IN Input Ra ANA IN Input Amplifier Gain Setting 00 01 10 11 Resistor Ratio (Rb/Ra) 40.1 / 40.1 47.0 / 33.2 53.5 / 26.7 59.2 / 21 Gain 1.0 1.414 2.0 2.82 Gain(2) (dB) 0 3 6 9 Note: Ra & Rb are in k NOTE: fCUTTOFF 1 2xRaCCOUP AUX IN Amplifier Gain Settings Setting 0 dB 3 dB 6 dB 9 dB (1) 0TLP Input VP-P(3) 0.694 0.491 0.347 0.245 CFG0 AXG1 0 0 1 1 AXG0 0 1 0 1 Gain(2) 1.00 1.41 2.00 2.82 Array In/Out VP-P 0.694 0.694 0.694 0.694 Speaker Out VP-P(4) 0.694 0.694 0.694 0.694 1. Gain from AUX IN to ANA OUT 2. Gain from AUX IN to ARRAY IN 3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping 4. Differential - 35 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.5. DIGITAL MODE 7.5.1. Erasing Digital Data The Digital Erase command can only erase an entire page at a time. This means that the D1 command only needs to include the 11-bit page address; the 5-bit for block address are left at 00000. Once a page has been erased, each block may be written separately, 64 bits at a time. But, if a block has been previously written then the entire page of 2048 bits must be erased in order to re-write (or change) a block. A sequence might be look like: - read the entire page - store it in RAM - change the desired bit(s) - erase the page - write the new data from RAM to the entire page 7.5.2. Writing Digital Data The Digital Write function allows the user to select a portion of the array to be used as digital memory. The partition between analog and digital memory is left up to the user. A page can only be either Digital or Analog, but not both. The minimum addressable block of memory in the digital mode is one block or 64 bits, when reading or writing. The address sent to the device is the 11-bit row (or page) address with the 5-bit scan (or block) address. However, one must send a Digital Erase before attempting to change digital data on a page. This means that even when changing only one of the 32 blocks, all 32 blocks will need to be rewritten to the page. Command Sequence: The chip enters digital mode by sending the ENTER DIGITAL MODE command from power down. Send the DIGITAL WRITE @ ADDR command with the row address. After the address is entered, the data is sent in one-byte packets followed by an I2C acknowledge generated by the chip. Data for each block is sent MSB first. The data transfer is ended when the master generates an I2C STOP condition. If only a partial block of data is sent before the STOP condition, "zero" is written in the remaining bytes; that is, they are left at the erase level. An erased page (row) will be read as all zeros. The device can buffer up to two blocks of data. If the device is unable to accept more data due to the internal write process, the SCL line will be held LOW indicating to the master to halt data transfer. If the device encounters an overflow condition, it will respond by generating an interrupt condition and an I2C Not Acknowledge signal after the last valid byte of data. Once data transfer is terminated, the device needs up to two cycles (64 us) to complete its internal write cycle before another command is sent. If an active command is sent before the internal cycle is finished, the part will hold SCL LOW until the current command is finished. After writing is complete, send the EXIT DIGITAL MODE command. - 36 - ISD5100 - SERIES 7.5.3. Reading Digital Data The Digital Read command utilizes the combined I2C command format. That is, a command is sent to the chip using the write data direction. Then the data direction is reversed by sending a repeated start condition, and the slave address with R/W set to 1. After this, the slave device (ISD5100Series) begins to send data to the master until the master generates a NACK. If the part encounters an overflow condition, the INT pin is pulled LOW. No other communication with the master is possible due to the master generating ACK signals. Digital Write and Digital Read can be done a "block" at a time. each Digital Read command sequence. Thus, only 64 bits need be read in 7.5.4. Example Command Sequences An explanation and graphical representation of the Erase, Write and Read operations are found below. Note: All sequences assumes that the chip is in power-down mode before the commands are sent. 7.5.4.1. Erase Digital Data Erase ===== I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0xc0) WaitACK WaitSCLHigh I2CStop I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0xd1) WaitACK WaitSCLHigh SendByte(row/256) - high address byte Publication Release Date: October, 2003 Revision 0.2 - Digital Erase Command - Write, Slave address zero - Enter Digital Mode Command - Write, Slave address zero - 37 - ISD5100 - SERIES WaitACK WaitSCLHigh SendByte(row%256) WaitACK WaitSCLHigh I2CStop repeat until the number of RAC pulses are one less than the number of rows to delete { wait RAC low WAIT RAC high } Note: If only one row is going to be erased, send the following STOP command immediately after ERASE command and skip the loop above I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0xc0) WaitACK WaitSCLHigh I2CStop wait until erase of the last row has completed { wait RAC low WAIT RAC high } I2CStart SendByte(0x80) WaitACK - Write, Slave address zero - Stop digital erase - Write, Slave address zero - low address byte - 38 - ISD5100 - SERIES WaitSCLHigh SendByte(0x40) WaitACK WaitSCLHigh I2Cstop Notes 1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address Byte will be ignored. 2. I2C bus is released while erase proceeds. Other devices may use the bus until it is time to execute the STOP command that causes the end of the Erase operation. 3. Host processor must count RAC cycles to determine where the chip is in the erase process, one row per RAC cycle. RAC pulses LOW for 0.25 millisecond at the end of each erased row. The erase of the "next" row begins with the rising edge of RAC. See the Digital Erase RAC timing diagram on page 51. 4. When the erase of the last desired row begins, the following STOP command (Command Byte = 80 hex) must be issued. This command must be completely given, including receiving the ACK from the Slave before the RAC pin goes HIGH at the end of the row. - Exit Digital Mode Command - 39 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES S SLAVE ADDRESS W A CON A P Erase starts on falling edge of Slave acknowledge S SLAVE ADDRESS W A D1 A DATA A DATA A P Note 2 Command Byte High Addr. Byte Low Addr. Byte "N" RAC cycles Last erased row Note Note S SLAVE ADDRESS W A 80 A P Command Byte S SLAVE ADDRESS W A 40h A P - 40 - ISD5100 - SERIES SUGGESTED FLOW FOR DIGITAL ERASE IN ISD5100-Series 80,C0 ENTER DIGITAL MODE TO ERASE MULTIPLE (n) PAGES (ROWS) 80,D1,nn,nn SEND ERASE COMMAND COMMANDS 80 = PowerUp or Stop C0 = Enter Digital Mode D1 = Erase Digital Page@ 40 = Exit Digital Mode NO COUNT RAC FOR n-1 RAC\ ~ 250 uS YES 80,C0 SEND STOP COMMAND BEFORE RAC SEND STOP COMMAND BEFORE NEXT RAC 80,C0 NO WAIT FOR RAC RAC\ ~ 125 uS WAIT FOR RAC NO RAC\ ~ 125 uS YES YES 80,40 EXIT DIGITAL MODE STOP COMMAND MUST BE FINISHED BEFORE RAC\ RISES 6/20/2002 BOJ Revision B DEVICE POWERS DOWN AUTOMATICALLY RAC\ SIGNAL 250 uS 1.25 ms 125 uS - 41 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.5.4.2. Write Digital Data Write ===== I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0xc0) WaitACK WaitSCLHigh I2CStop I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0xc9) WaitACK WaitSCLHigh SendByte(row/256) WaitACK WaitSCLHigh SendByte(row%256) WaitACK WaitSCLHigh repeat until all data is sent { SendByte(data) WaitACK() WaitSCLHigh() } I2CStop - send data byte - low address byte - high address byte - Write Digital Data Command - Write, Slave address zero - Enter Digital Mode Command - Write, Slave address zero - 42 - ISD5100 - SERIES I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0x40) WaitACK WaitSCLHigh I2CStop - Exit Digital Mode Command - Write, Slave address zero S SLAVE ADDRESS W A CON A P S SLAVE ADDRESS W A C9h A DATA A DATA A Command Byte High Addr. Byte Low Addr. Byte DATA A DATA A ~ ~ ~ ~ DATA A P S SLAVE ADDRESS W A 40h A P - 43 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES S U G G E S T E D F L O W F O R D IG IT A L W R IT E IN IS D 5 1 0 0 -S e rie s 8 0 ,C 0 E N T E R D IG IT A L MODE 8 0 ,C 9 ,n n ,n n S E N D W R IT E COMMAND W / START ADDRESS C O M M AN D S 8 0 = P o w e rU p o r S to p C 0 = E n te r D ig ita l M o d e C 9 = W rite D ig ita l P a g e @ 4 0 = E x it D ig ita l M o d e SEND DATA BYTE (S E N D NE XT BYTE) W A IT fo r S C L H IG H NO BYTE COUNTER =256? YES 8 0 ,4 0 E X IT D IG IT A L MODE 6 /2 4 /2 0 0 2 B O J R e vis io n N /C D E V IC E POW ERS DOW N A U T O M A T IC A L L Y - 44 - ISD5100 - SERIES 7.5.4.3. Read Digital Data Read ===== I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0xc0) WaitACK WaitSCLHigh I2CStop I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0xe1) WaitACK WaitSCLHigh SendByte(row/256) WaitACK WaitSCLHigh() SendByte(row%256) WaitACK WaitSCLHigh I2CStart SendByte(0x81) - Send repeat start command - Read, Slave address zero - low address byte - high address byte - Read Digital Data Command - Write, Slave address zero - Enter Digital Mode - Write, Slave address zero repeat until all data is read { data = ReadByte() SendACK WaitSCLHigh - send clocks to read data byte - send NACK on the last byte - The only flow control available Publication Release Date: October, 2003 Revision 0.2 - 45 - ISD5100 - SERIES } I2CStop() I2CStart SendByte(0x80) WaitACK WaitSCLHigh SendByte(0x40) WaitACK WaitSCLHigh I2CStop S SLAVE ADDRESS W A CON A P - Exit Digital Mode - Write, Slave address zero S SLAVE ADDRESS W A E1h A DATA A DATA A Command Byte High Addr. Byte Low Addr. Byte S SLAVE ADDRESS W A 40h ~ ~ S SLAVE ADDRESS R A DATA A DATA A ~ ~ DATA N P A P - 46 - ISD5100 - SERIES S U G G E S T E D F L O W F O R D IG IT A L R E A D IN IS D 5 1 0 0 -S e rie s 8 0 ,C 0 E N T E R D IG IT A L MODE 8 0 ,E 1 ,n n ,n n SEND READ COMMAND W / START ADDRESS C O M M AN D S 8 0 = P o w e rU p o r S to p C 0 = E n te r D ig ita l M o d e E 1 = R e a d D ig ita l P a g e @ 4 0 = E x it D ig ita l M o d e READ DATA BYTE (R E A D N E XT BYTE) W A IT fo r S C L H IG H NO BYTE COUNTER =256? YES 8 0 ,4 0 E X IT D IG IT A L MODE 6 /2 4 /2 0 0 2 B O J R e vis io n N /C D E V IC E POW ERS DOW N A U T O M A T IC A L L Y - 47 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.6. PIN DETAILS 7.6.1. Digital I/O Pins SCL (Serial Clock Line) The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over the Serial Data Line. SDA (Serial Data Line) The Serial Data Line carries the data between devices on the I2C interface. Data must be valid on this line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bi-directional line requiring a pull-up resistor to Vcc. RAC (Row Address Clock) RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency, the duration of this period is 256 ms. There are 2048 pages of memory in the ISD5116 devices, 1024 pages in the ISD5108, and 572 pages in the ISD5104. RAC stays HIGH for 248 ms and stays LOW for the remaining 8 ms before it reaches the end of the page. 1 ROW RAC Waveform During 8 KHz Operation 256 msec TRAC 8 msec TRACL The RAC pin remains HIGH for 500 sec and stays LOW for 15.6 sec under the Message Cueing mode. See the Timing Parameters table on page 64 for RAC timing information at other sample rates. When a record command is first initiated, the RAC pin remains HIGH for an extra TRACML period, to load sample and hold circuits internal to the device. The RAC pin can be used for message management techniques. 1 ROW RAC Waveform During Message Cueing @ 8KHz Operation 500 usec TRACM 15.6 us TRACML - 48 - ISD5100 - SERIES RAC Waveform During Digital Erase @ 8kHz Operation 1.25 ms TRACE .25 ms TRACEL INT (Interrupt) INT is an open drain output pin. The ISD5100 Series interrupt pin goes LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ STATUS instruction that will give a status byte out the SDA line. XCLK (External Clock Input) The external clock input for the ISD5100 Series product has an internal pull-down device. Normally, the ISD5100 Series are operated at one of four internal rates selected for its internal oscillator by the Sample Rate Select bits. If greater precision is required, the device can be clocked through the XCLK pin at 4.096 MHz as described in section 7.4.3 on page 32. Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for optimum performance, maintain the external clock at 4.096 MHz AND set the Sample Rate Configuration bits to one of the four values to properly set the filters to the correct cutoff frequency as described in section 7.4.3 on page 32. The duty cycle on the input clock is not critical, as the clock is immediately divided by two internally. If the XCLK is not used, this input should be connected to VSSD. External Clock Input Table ISD5116 Duration (Minutes) 8.73 10.9 13.1 17.5 ISD5108 Duration (Minutes) 4.36 5.45 6.55 8.75 ISD5104 Duration (Minutes) 2.18 2.72 3.27 4.37 ISD5102 Duration (Minutes) 1.08 1.35 1.63 2.18 Sample Rate (kHz) 8.0 6.4 5.3 4.0 Required Clock (kHz) 4096 4096 4096 4096 FLD1 FLD0 Filter Knee (kHz) 3.4 2.7 2.3 1.7 0 0 1 1 0 1 0 1 - 49 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES A0, A1 (Address Pins) These two pins are normally strapped for the desired address that the ISD5100 Series will have on the I2C serial interface. If there are four of these devices on the bus, then each must be strapped differently in order to allow the Master device to address them individually. The possible addresses range from 80h to 87h, depending upon whether the device is being written to, or read from, by the host. The ISD5100 Series have a 7-bit slave address of which only A0 and A1 are pin programmable. The eighth bit (LSB) is the R/W bit. Thus, the address will be 1000 0xy0 or 1000 0xy1. (See the table in section 7.3.1 on page 13.) 7.6.2. Analog I/O Pins MIC+, MIC(Microphone Input +/-) The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the ANA OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6 dB so a 208 mV p-p signal across the differential microphone inputs would give 416 mV p-p across the ANA OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mV p-p into the storage array from a typical electret microphone output of 2 to 20 mV p-p. The input impedance is typically 10k. 1.5k Internal to the device MIC+ 220 F + 1.5k CCOUP=0.1 F Ra=10k AGC 0.1 1.5k 6 dB FTHRU Electret Microphone WM-54B Panasonic 10k MIC IN MIC- NOTE: fCUTOFF= 1 2RaCCOUP ANA OUT+, ANA OUT- (Analog Output +/-) This differential output is designed to go to the microphone input of the telephone chip set. It is designed to drive a minimum of 5 k between the "+" and "-" pins to a nominal voltage level of 694 mV p-p. Both pins have DC bias of approximately 1.2 VDC. The AC signal is superimposed upon this analog ground voltage. These pins can be used single-ended, getting only half the voltage. Do NOT ground the unused pin. - 50 - ISD5100 - SERIES ACAP (AGC Capacitor) This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It should have a 4.7 F capacitor connected to ground. It cannot be left floating. This is because the capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the amount of noise present in the output during quiet pauses. Tying this pin to ground gives maximum gain; tying it to VCCA gives minimum gain for the AGC amplifier but cancels the AutoMute function. SP +, SP(Speaker +/-) This is the speaker differential output circuit. It is designed to drive an 8 speaker connected across the speaker pins up to a maximum of 23.5 mW RMS power. This stage has two selectable gains, 1.32 and 1.6, which can be chosen through the configuration registers. These pins are biased to approximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT ground the unused pin. AUX OUT (Auxiliary Output) The AUX OUT is an additional audio output pin to be used, for example, to drive the speaker circuit in a "car kit." It drives a minimum load of 5k and up to a maximum of 1V p-p. The AC signal is superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load. OUT PUT MUX VOL Car Kit AUX OUT (1 Vp-p Max ) ANA IN AMP SP + FILT O SP - 2 ( OP A1, OPA0) 2 ( OP S1,OP S0) Speak er SUM2 OPS1 0 0 1 1 15 AI G1 OPS0 0 1 0 1 14 13 SOURCE VOL ANA IN FILTO SUM2 12 11 10 OPS1 0 0 1 1 OPA0 0 1 0 1 1 0 SPKR DRIVE Power Down 3.6 Vp.p @150 23.5 mWatt @ 8 Power Down AUX OUT Power Down Power Down Power Down 1 Vp.p Max @ 5K 9 8 7 6 5 4 3 2 AI G0 AI P D AXG1 AX G0 AXP D I NS0 AOS2 AOS1 AOS 0 AOPD OP S1 OPS0 OP A1 OPA0 VLPD CFG0 - 51 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES ANA IN (Analog Input) The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I2C interface) to the speaker output, the array input or to various other paths. This pin is designed to accept a nominal 1.11 V p-p when at its minimum gain (6 dB) setting. There is additional gain available, if required, in 3 dB steps, up to 15 dB. The gain settings are controlled from the I2C interface. ANA IN Input Modes Internal to the device Rb CCOUP = 0.1 iF ANA IN Input Ra Gain Setting 00 01 10 11 Resistor Ration (Rb/Ra) 63.9 / 102 77.9 / 88.1 92.3 / 73.8 106 / 60 Gain 0.625 0.88 1.25 1.77 Gain2 (dB) -4.1 -1.1 1.9 4.9 ANA IN Input Amplifier Note: Ra & Rb are in k NOTE: fCUTTOFF 1 2xRaCCCUP ANA IN Amplifier Gain Settings Setting (1) 0TLP Input VP-P(3) 1.110 0.785 0.555 0.393 CFG0 AIG1 0 0 1 1 AIG0 0 1 0 1 Gain(2) 0.625 0.883 1.250 1.767 Array In/Out VP-P 0.694 0.694 0.694 0.694 Speaker Out VP-P(4) 2.22 2.22 2.22 2.22 6 dB 9 dB 12 dB 15 dB 1. 2. 3. 4. Gain from ANA IN to SP+/Gain from ANA IN to ARRAY IN 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping Speaker Out gain set to 1.6 (High). (Differential) - 52 - ISD5100 - SERIES AUX IN (Auxiliary Input) The AUX IN is an additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone "car kit." This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the AUX IN Amplifier Gain Settings table on page 56. Additional gain is available in 3 dB steps (controlled by the I2C interface) up to 9 dB. AUX IN Input Modes Internal to the device Rb CCOUP = 0.1 iF AUX IN Input Ra ANA IN Input Amplifier Gain Setting 00 01 10 11 Resistor Ratio (Rb/Ra) 40.1 / 40.1 47.0 / 33.2 53.5 / 26.7 59.2 / 21 Gain 1.0 1.414 2.0 2.82 Gain(2) (dB) 0 3 6 9 NOTE: fCUTTOFF 1 2xRaCCCUP Note: Ra & Rb are in k AUX IN Amplifier Gain Settings Setting 0 dB 3 dB 6 dB 9 dB 1. 2. (1) 0TLP Input VP-P(3) 0.694 0.491 0.347 0.245 CFG0 AXG1 0 0 1 1 AXG0 0 1 0 1 Gain(2) 1.00 1.41 2.00 2.82 Array In/Out VP-P 0.694 0.694 0.694 0.694 Speaker Out VP-P(4) 0.694 0.694 0.694 0.694 Gain from AUX IN to ANA OUT Gain from AUX IN to ARRAY IN 3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping 4. Differential - 53 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 7.6.3. Power and Ground Pins VCCA, VCCD (Voltage Inputs) To minimize noise, the analog and digital circuits in the ISD5100 Series devices use separate power busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible and decouple both supplies as near to the package as possible. VSSA, VSSD (Ground Inputs) The ISD5100 Series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins should be tied together as close to the package as possible and connected through a lowimpedance path to power supply ground. The digital ground (VSSD) pin should be connected through a separate low impedance path to power supply ground. These ground paths should be large enough to ensure that the impedance between the VSSA pins and the VSSD pin is less than 3. The backside of the die is connected to VSSD through the substrate resistance. In a chip-on-board design, the die attach area must be connected to VSSD. NC (Not Connect) These pins should not be connected to the board at any time. Connection of these pins to any signal, ground or VCC, may result in incorrect device behavior or cause damage to the device. - 54 - ISD5100 - SERIES 7.6.4. PCB Layout Examples For SOIC package : PC board traces and the three chip capacitors are on the bottom side of the board. 1 Note 2 O O O O O O O O O O O O O O C1 C2 Note 3 Note V S S D (Digital G round) 1 Note 1: V SSD traces should be kept separated back to the V SS supply feed point.. Note 2: V CCD traces should be kept separate back to the V CC Supply feed point. Note 3: The Digital and Analog grounds tie together at the power supply. The V CCA and V CCD supplies will also need filter capacitors per good engineering practice (typ. 50 to 100 uF). C3 O O O O O O O O O O O O O O XCLK V C C D V SS A C1=C2=C3=0.1 uF chip Capacitors To V CC A Analog Ground Note 3 For TSOP package : 1 VSSA Note [2] VCCA VCCD VCCD VSSA VCCA VCCD Note [1] VSSD Note [3] VSSD VSSD VSSA VSSA Notes: [1] [2] [3] VSSD traces should be kept separated back to the VSS supply feedpoint. VCCD traces should be kept separate back to the VCC supply feedpoint. Digital and Analog grounds tie together at power supply. The VCCA and VCCD supplies will also need filter capacitors per good engineering practice (typ. 50 to 100 uF). - 55 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 8.TIMING DIAGRAMS 8.1. I2C TIMING DIAGRAM STOP START t t SU-DAT t f r SDA SCL t t f t LOW HIGH t t SCLK SU-STO - 56 - ISD5100 - SERIES I2C INTERFACE TIMING STANDARD-MODE PARAMETER SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus-free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) SYMBOL MIN. 0 4.0 MAX. 100 - FAST-MODE MIN. 0 0.6 MAX. 400 UNIT kHz s fSCL tHD-STA tLOW tHIGH tSU-STA tSU-DAT tr tf tSU-STO tBUF Cb VnL 4.7 4.0 4.7 250 4.0 4.7 0.1 VDD 1000 300 400 - 1.3 0.6 0.6 100(1) 20 + 0.1Cb (2) 300 300 400 - s s s ns ns ns s s pF V 20 + 0.1Cb(2) 0.6 1.3 0.1 VDD VnH 0.2 VDD - 0.2 VDD - V 1. A Fast-mode I2C-interface device can be used in a Standard-mode I2C-interface system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA 2 line; tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I C -interface specification) before the SCL line is released. 2. Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed. - 57 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 8.2. PLAYBACK AND STOP CYCLE tSTART SDA PLAY AT ADDR STOP tSTOP SCL DATA CLOCK PULSES STOP ANA IN ANA OUT - 58 - ISD5100 - SERIES 8.3. EXAMPLE OF POWER UP COMMAND (FIRST 12 BITS) - 59 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 9. ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)(1) Condition Junction temperature Storage temperature range Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering VCC - VSS 1. Value 150 C -650C to +1500C (VSS - 0.3V) to (VCC + 0.3V) (VSS - 1.0V) to (VCC + 1.0V) 3000C -0.3V to +5.5V 0 - 10 seconds) Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. ABSOLUTE MAXIMUM RATINGS (DIE)(1) Condition Junction temperature Storage temperature range Voltage Applied to any pad VCC - VSS 1. Value 150 C -650C to +1500C (VSS - 0.3V) to (VCC + 0.3V) -0.3V to +5.5V 0 Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. - 60 - ISD5100 - SERIES OPERATING CONDITIONS (PACKAGED PARTS) Condition Commercial operating temperature range Extended operating temperature Supply voltage (VCC)(2) Ground voltage (VSS) 1 Value (1) 0 C to +70 C -200C to +700C -400C to +850C +2.7V to +3.3V 0V 0 0 (1) Industrial operating temperature(1) (3) . Case temperature 2. VCC = VCCA = VCCD 3. VSS = VSSA = VSSD OPERATING CONDITIONS (DIE) Condition Die operating temperature range Supply voltage (VCC) (2) (3) (1) 0 0 Value 0 C to +50 C +2.7V to +3.3V 0V Ground voltage (VSS) 1. Case temperature 2. VCC = VCCA = VCCD 3. VSS = VSSA = VSSD - 61 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS Symbol VIL VIH VOL VIL2V VIH2V VOL1 VOH ICC Parameters Input Low Voltage Input High Voltage SCL, SDA Voltage Input low interface Output voltage for Low 2V 1.6 0.4 VCC - 0.4 15 30 12 1 25 40 15 10 1 VCC x 0.8 0.4 0.4 Min(2) Typ(1) Max(2) VCC x 0.2 Unit s V V V V V V V mA mA mA A A IOL = 3 A Apply only SCL, SDA Apply only SCL, SDA IOL = 1 mA IOL = -10 A No Load(3) No Load(3) No Load(3) (3) to to Conditions Input high voltage for 2V interface RAC, INT Output Low Voltage Output High Voltage VCC Current (Operating) - Playback - Record - Feedthrough ISB IIL VCC Current (Standby) Input Leakage Current 1. 2. Typical values: TA = 25C and Vcc = 3.0 V. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. VCCA and VCCD summed together. 3. - 62 - ISD5100 - SERIES 10.2. TIMING PARAMETERS Symbol FS Parameters Sampling Frequency Min(2) Typ(1) 8.0 6.4 5.3 4.0 FCF Filter Knee 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TREC Record Duration 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TPLAY Playback Duration 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TPUD Power-Up Delay 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TSTOP OR PAUSE Max(2) Units kHz kHz kHz kHz kHz kHz kHz kHz Conditions (5) (5) (5) (5) Knee Point Knee Point (3)(7) 3.4 2.7 2.3 1.7 ISD5116 ISD5108 ISD5104 ISD5102 Knee Point(3)(7) (3)(7) Knee Point(3)(7) (6) (6) (6) (6) 8.73 10.9 13.1 17.5 ISD5116 4.36 5.45 6.55 8.75 ISD5108 2.18 2.72 3.27 4.37 ISD5104 1.08 1.35 1.63 2.18 ISD5102 min min min min 8.73 10.9 13.1 17.5 4.36 5.45 6.55 8.75 2.18 2.72 3.27 4.37 1 1 1 1 1.08 1.35 1.63 2.18 min min min min (6) (6) (6) (6) msec msec msec msec Stop or Pause Record or Play 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) 32 40 48 64 256 320 384 msec msec msec msec msec msec msec (9) (9) (9) TRAC RAC Clock Period 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) - 63 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 4.0 kHz (sample rate) TRACL RAC Clock Low Time 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TRACM RAC Clock Period in Message Cueing Mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TRACML RAC Clock Low Time in Message Cueing Mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TRACE RAC Clock Period Digital Erase Mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) TRACEL RAC Clock Low Time in Digital Erase mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) THD Total Harmonic Distortion ANA IN to ARRAY, ARRAY to SPKR 1 1 2 2 % % 0.25 0.31 0.37 0.50 msec msec msec msec @1 kHz at 0TLP, sample rate = 5.3 kHz in 1.25 1.56 1.87 2.50 msec msec msec msec 15.6 19.5 23.4 31.2 sec sec sec sec 500 625 750 1000 sec sec sec sec 8 10 12.1 16 msec msec msec msec 512 msec (9) - 64 - ISD5100 - SERIES 10.3. ANALOG PARAMETERS MICROPHONE INPUT(14) Symbol VMIC+/VMIC (0TLP) Parameters MIC +/- Input Voltage MIC +/- input reference transmission level point (0TLP) Gain from MIC +/- input to ANA OUT MIC +/- Gain Tracking Microphone input resistance Microphone AGC Amplifier Range Min(2) Typ(1)(14) 208 Max(2) 300 Units mV mV Conditions Peak-to-Peak(4)(8) Peak-to-Peak(4)(10) AMIC AMIC (GT) RMIC AAGC 5.5 6.0 6.5 dB (4) (0TLP) 1 kHz at VMIC +/-0.1 10 6 40 dB k dB 1 kHz, +3 to -40 dB 0TLP Input MICpins and MIC+ mV Over 3-300 Range ANA IN(14) Symbol VANA IN VANA IN (0TLP) AANA IN (sp) AANA IN (AUX OUT) AANA IN (GA) AANA IN (GT) Parameters ANA IN Input Voltage ANA IN Voltage (0TLP) Input Min(2) Typ(1)(14) Max(2) 1.6 Units V V dB dB Conditions Peak-to-Peak (6 dB gain setting) Peak-to-Peak (6 dB gain setting)(10) 4 Steps of 3 dB 4 Steps of 3 dB (11) 1000 Hz, +3 to -45 dB 0TLP Input, 6 dB setting Depending on ANA IN Gain 1.1 +6 to +15 -4 to +5 -0.5 +/-0.1 +0.5 Gain from ANA IN to SP+/Gain from ANA IN to AUX OUT ANA IN Gain Accuracy ANA IN Gain Tracking dB dB RANA IN ANA IN Input Resistance (6 dB to +15 dB) 10 to 100 k - 65 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES AUX IN(14) Symbol VAUX IN VAUX IN (0TLP) AAUX IN (ANA OUT) AAUX IN (GA) AAUX IN (GT) Parameters AUX IN Input Voltage AUX IN Voltage (0TLP) Input Min(2) Typ(1)(14) Max(2) 1.0 Units V mV dB Conditions Peak-to-Peak (0 dB gain setting) Peak-to-Peak (0 dB gain setting) 4 Steps of 3 dB (11) 1000 Hz, +3 to -45 dB 0TLP Input, 0 dB setting Depending on AUX IN Gain 694.2 0 to +9 -0.5 +/-0.1 +0.5 Gain from AUX IN to ANA OUT AUX IN Gain Accuracy AUX IN Gain Tracking dB dB RAUX IN AUX IN Input Resistance 10 to 100 k SPEAKER OUTPUTS(14) Symbol VSPHG Parameters SP+/- Output Voltage (High Gain Setting) Min(2) Typ(1)(14) Max(2) 3.6 Units V Conditions Peak-to-Peak, differential load = 150, OPA1, OPA0 = 01 OPA1, OPA0 = 10 OPA1, OPA0 = 01 RSPLG RSPHG CSP VSPAG VSPDCO SP+/- Output (Low Gain) SP+/- Output (High Gain) Load Load Imp. Imp. 8 70 150 100 1.2 +/-100 pF VDC mV DC dB dB SP+/- Output Load Cap. SP+/- Output Bias Voltage (Analog Ground) Speaker Output DC Offset With ANA IN to Speaker, ANA IN AC coupled to VSSA Speaker Load (12)(13) 150 = ICNANA IN/(SP+/-) CRT(SP+/-)/ANA OUT ANA IN to SP+/Channel Noise Idle -65 -65 SP+/- to ANA OUT Cross Talk 1 kHz 0TLP input to ANA IN, with MIC+/- and AUX IN AC coupled to VSS, and measured at ANA OUT feed through mode (12) Measured with a 1 kHz, 100 mV p-p sine wave input at PSRR Power Ratio Supply Rejection -55 dB - 66 - ISD5100 - SERIES VCC and VCC pins FR Frequency Response (3003400 Hz) +0.5 dB With 0TLP input to ANA IN, 6 dB setting (12) Guaranteed design POUTLG SINAD Power Output (Low Gain Setting) SINAD ANA IN to SP+/23.5 62.5 mW RMS dB by Differential load at 8 0TLP ANA In input minimum gain, 150 load (12)(13) ANA OUT (14) Symbol SINAD SINAD ICONIC/ANA OUT ICN OUT Parameters SINAD, MIC IN to ANA OUT SINAD, AUX IN to ANA OUT (0 to 9 dB) Idle Channel Microphone Noise - Min (2) 62.5 62.5 Type (1)(14) Max (2) Units dB dB Conditions Load = 5k(12)(13) Load = 5k(12)(13) Load = 5k(12)(13) Load = 5k(12)(13) Measured with a 1 kHz, 100 mV P-P sine wave to VCCA, VCCD pins Inputs AC coupled to VSSA Inputs AC coupled to VSSA Differential Load 0TLP input to MIC+/in feedthrough mode. 0TLP input to AUX IN in feedthrough mode(12) -65 -65 -40 dB dB dB AUX IN/ANA Idle Channel Noise - AUX IN (0 to 9 dB) Power Ratio Supply Rejection PSRR (ANA OUT) VBIAS VOFFSET RL FR ANA OUT+ and ANA OUTANA OUT+ to ANA OUTMinimum Load Impedance Frequency Response (3003400 Hz) 5 1.2 +/- 100 VDC mV DC k +0.5 dB CRTANA OUT/(SP+/-) ANA OUT to SP+/- Cross Talk -65 dB 1 kHz 0TLP output from ANA OUT, with ANA IN AC coupled to VSSA, and measured at SP+/-(12) - 67 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES CRTANA OUT OUT/AUX ANA OUT to AUX OUT Cross Talk -65 dB 1 kHz 0TLP output from ANA OUT, with ANA IN AC coupled to VSSA, and measured at AUX OUT(12) AUX OUT(14) Symbol VAUX OUT RL CL VBIAS SINAD Parameters AUX OUT - Maximum Output Swing Minimum Load Impedance Maximum Load Capacitance AUX OUT SINAD - ANA IN to AUX OUT Idle Channel Noise - ANA IN to AUX OUT AUX OUT to ANA OUT Cross Talk Min(2) Typ(1(14)) Max(2) 1.0 Units V K Conditions 5k Load 5 100 1.2 62.5 pF VDC dB 0TLP ANA IN input, minimum gain, 5k load(12)(13) Load=5k(12)(13) 1 kHz 0TLP input to ANA IN, with MIC +/- and AUX IN AC coupled to VSSA, measured at SP+/-, load = 5k. Referenced to nominal 0TLP @ output ICN(AUX OUT) CRTAUX OUT OUT/ANA -65 -65 dB dB VOLUME CONTROL(14) Symbol AOUT Parameters Output Gain Min(2) Typ(1)(14) -28 to 0 Max(2) Units dB Conditions 8 steps of 4 dB, referenced to output ANA IN 1.0 kHz 0TLP, 6 dB gain setting measured differentially at SP+/- Tolerance for each step -1.0 +1.0 dB - 68 - ISD5100 - SERIES Conditions 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical values: TA = 25C and Vcc = 3.0V. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions). Differential input mode. Nominal differential input is 208 mV p-p. (0TLP) Sampling frequency can vary as much as -6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions). Playback and Record Duration can vary as much as -6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions). Filter specification applies to the low pass filter. For optimal signal quality, this maximum limit is recommended. When a record command is sent, TRAC = TRAC + TRACL on the first page addressed. The maximum signal level at any input is defined as 3.17 dB higher than the reference transmission level point. (0TLP) This is the point where signal clipping may begin. Measured at 0TLP point for each gain setting. See the ANA IN table and AUX IN table on pages 54 and 55 respectively. 0TLP is the reference test level through inputs and outputs. See the ANA IN table and AUX IN table on pages 54 and 55 respectively. Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth. For die, only typical values are applicable. 14. 10.4. CHARACTERISTICS OF THE I2C SERIAL INTERFACE The I2C interface is for bi-directional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not busy. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. - 69 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES SDA SCL data line stable; data valid changed of data allowed Bit transfer on the I2C-Bus Start and stop conditions Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). SDA SDA SCL S START condition P STOP condition SCL System configuration Definition of START and STOP conditions A device generating a message is a `transmitter'; a device receiving a message is the `receiver'. Th System Configuration A device generating a message is a `transmitter'; a device receiving a message is the `receiver'. The device that controls the message I sthe `master' and the devices that are controlled by the master are the `slaves'. - 70 - ISD5100 - SERIES MICROCONTROLLER LCD DRIVER STATIC RAM OR EEPROM SDA SCL GATE ARRAY ISD 5116 Example of an I C-bus configuration using two microcontrollers 2 Acknowledge The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the interface bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. In addition, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (setup and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition dock pulse for acknowledgement 1 2 8 9 Acknowledge on the I C-bus 2 - 71 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 10.5. I2C PROTOCOL Since the I2C protocol allows multiple devices on the bus, each device must have an address. This address is known as a "Slave Address". A Slave Address consists of 7 bits, followed by a single bit that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read cycle, which indicates that the data is being sent from the device being addressed to the current bus master. For example, the valid Slave Addresses for the ISD5100 Series device, for both Write and Read cycles, are shown in section 7.3.1 on page 13 of this datasheet. Before any data is transmitted on the I2C interface, the current bus master must address the slave it wishes to transfer data to or from. The Slave Address is always sent out as the 1st byte following the Start Condition sequence. An example of a Master transmitting an address to a ISD5100 Series slave is shown below. In this case, the Master is writing data to the slave and the R/W bit is "0", i.e. a Write cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge bits. The following example details the transfer explained in section 7.3.1-2-3 on pages 13-20 of this datasheet. Master Transmits to Slave Receiver (Write) Mode acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS WA COMMAND BYTE A High ADDR. BYTE A Low ADDR. BYTE A P Start Bit R/W Stop Bit A common procedure in the ISD5100 Series is the reading of the Status Bytes. The Read Status condition in the ISD5100 Series is triggered when the Master addresses the chip with its proper Slave Address, immediately followed by the R/W bit set to a "1" and without the Command Byte being sent. This is an example of the Master sending to the Slave, immediately followed by the Slave sending data back to the Master. The "N" not-acknowledge cycle from the Master ends the transfer of data from the Slave. The following example details the transfer explained in section 7.3.1 on page 13 of this datasheet. - 72 - ISD5100 - SERIES Master Reads from Slave immediately after first byte (Read Mode) acknowledgement from slave From Slave S SLAVE ADDRESS R A STATUS W ORD A From Slave High ADDR. BYTE A From Slave Low ADDR BYTE N P From Master Start Bit From Master R/W From Master acknowledgement from Master acknowledgement from Master Stop Bit From Master not-acknowledged from Master Another common operation in the ISD5100 Series is the reading of digital data from the chip's memory array at a specific address. This requires the I2C interface Master to first send an address to the ISD5100 Series Slave device, and then receive data from the Slave in a single I2C operation. To accomplish this, the data direction R/W bit must be changed in the middle of the command. The following example shows the Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to the ISD5100-Series, and then immediately changing the data direction and reading some number of bytes from the chip's digital array. An unlimited number of bytes can be read in this operation. The "N" not-acknowledge cycle from the Master forces the end of the data transfer from the Slave. The following example details the transfer explained in section 7.5.4 on page 47 of this datasheet. Master Reads from the Slave after setting data address in Slave (Write data address, READ Data) acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave S SLAVE ADDRESS WA COMMAND BYTE A High ADDR. BYTE A Low ADDR. BYTE A Start Bit From Master R/W From Master acknowledgement from slave From Slave S SLAVE ADDRESS R A 8 BITS of DATA A From Slave 8 BITS of DATA A From Slave 8 BITS of DATA N P From Master Start Bit From Master R/W From Master acknowledgement from Master acknowledgement from Master not-acknowled from Master Stop Bit From Master - 73 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 11. TYPICAL APPLICATION CIRCUIT Recording via Microphone 1 To C I2C Interface & Address Setting VCC 1.5K 1.5K 220 F 0.1F 2 3 4 SCL SDA A1 A0 RAC INT 24 25 To C I/O for message management (optional) VCC 8 VCCD MIC+ Electret microphone 0.1F 10 51XX MICACAP VCCD VCCA VSSD VSSD VSSA VSSA VSSA SP+ SP- 27 28 17 5 6 9 15 23 0.1F 0.1F 1.5K 4.7F 13 16 14 SOIC / PDIP Please see web site www.winbond-usa.com for updates. - 74 - ISD5100 - SERIES 12. PACKAGE SPECIFICATION 12.1. 28-LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1 A A B B 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 G G 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 F C E E D H H I J J Plastic Thin Small Outline Package (TSOP) Type 1 Dimensions INCHES M in A B C D E F G H I J Note: 0.037 0 0.020 0.004 0 M ILLIM ETERS M ax 0.535 0.469 0.319 0.006 0.011 0.041 6 0.028 0.008 0 Nom 0.528 0.465 0.315 0.009 0.0217 0.039 3 0.022 0 M in 13.20 11.70 7.90 0.05 0.17 0.95 0 0.50 0.10 0 Nom 13.40 11.80 8.00 0.22 0.55 1.00 3 0.55 0 M ax 13.60 11.90 8.10 0.15 0.27 1.05 6 0.70 0.21 0 0.520 0.461 0.311 0.002 0.007 Lead coplanarity to be within 0.004 inches. - 75 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 12.2. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2345 6 7 8 9 10 11 12 13 14 A G C B D E F H Plastic Small Outline Integrated Circuit (SOIC) Dimensions INCHES Min A B C D E F G H Note: 0.400 0.024 0.701 0.097 0.292 0.005 0.014 Nom 0.706 0.101 0.296 0.009 0.016 0.050 0.406 0.032 0.410 0.040 10.16 0.61 Max 0.711 0.104 0.299 0.0115 0.019 Min 17.81 2.46 7.42 0.127 0.35 MILLIMETERS Nom 17.93 2.56 7.52 0.22 0.41 1.27 10.31 0.81 10.41 1.02 Max 18.06 2.64 7.59 0.29 0.48 Lead coplanarity to be within 0.004 inches. - 76 - ISD5100 - SERIES 12.3. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP) Plastic Dual Inline Package (PDIP) (P) Dimensions INCHES Min 1.445 0.065 0.600 0.530 0.015 0.125 0.015 0.055 0.008 0.070 0 Nom 1.450 0.150 0.070 0.540 Max 1.455 0.075 0.625 0.550 0.19 0.135 0.022 0.065 0.012 0.080 15 Min 36.70 1.65 15.24 13.46 0.38 3.18 0.38 1.40 0.20 1.78 0 MILLIMETERS Nom 36.83 3.81 1.78 13.72 Max 36.96 1.91 15.88 13.97 4.83 3.43 0.56 1.65 0.30 2.03 15 A B1 B2 C1 C2 D D1 E F G H J S 0 0.018 0.060 0.100 0.010 0.075 0.46 1.52 2.54 0.25 1.91 - 77 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 12.4 ISD5116 DIE INFORMATION VSSD VSSD SDA A0 VCCD SCL INT VCCD XCLK A1 RAC VSSA ISD5116 Device Die Dimensions X: 4125 m Y: 8030 m Die Thickness [3] 292.1 m 12.7 m Pad Opening Single pad: 90 x 90 m Double pad: 180 x 90 m ISD5116 VSSA MIC + MIC - ANA OUT - SP ACAP ANA OUT + VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. 2. 3. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or damage may occur. Double bond recommended, if treated as single doubled-pad. This figure reflects the current die thickness. Please contact Winbond as this thickness may change in the future. - 78 - ISD5100 - SERIES ISD5116 Pad Coordinates (with respect to die center in m) Pad VSSA RAC Pad Name Analog Ground Row Address Clock Interrupt External Clock Input Digital Supply Voltage Digital Supply Voltage Serial Clock Line Address 1 Serial Data Address Address 0 Digital Ground Digital Ground Analog Ground Non-inverting Microphone Input Inverting Microphone Input Non-inverting Analog Output Inverting Analog Output AGC/AutoMute Cap Speaker Negative Analog Ground Analog Ground Speaker Positive Analog Supply Voltage Analog Supply Voltage Analog Input Auxiliary Input Auxiliary Output X Axis 1879.45 1536.20 787.40 475.60 288.60 73.20 -201.40 -560.90 -818.20 -1369.40 -1671.30 -1842.90 -1948.00 -1742.20 -1509.70 -1248.00 -913.80 -626.50 -130.70 202.90 292.90 626.50 960.10 1050.10 1257.40 1523.00 1767.20 Y Axis 3848.65 3848.65 3848.65 3848.65 3848.65 3848.65 3848.65 3848.65 3848.65 3848.65 3848.65 3848.65 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 -3841.60 INT XCLK VCCD VCCD SCL A1 SDA A0 VSSD VSSD VSSA MIC+ MICANA OUT+ ANA OUTACAP SPVSSA VSSA SP+ VCCA VCCA ANA IN AUX IN AUX OUT - 79 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 12.5 ISD5108 DIE INFORMATION VSSD VSSD SDA SCL VCCD INT A1 VCCD XCLK A0 RAC VSSA ISD5108 Device Die Dimensions (include scribe line) X: 4230 m Y: 6090 m Die Thickness [3] 292.1 m 12.7 m Pad Opening Single pad: 90 x 90 m Double pad: 180 x 90 m ISD5108 VSSA MIC + MIC ANA OUT SP ANA OUT + ACAP VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. 2. 3. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or damage may occur. Double bond recommended, if treated as single doubled-pad. This figure reflects the current die thickness. Please contact Winbond as this thickness may change in the future. - 80 - ISD5100 - SERIES ISD5108 Pad Coordinates (with respect to die center in m) Pad VSSA RAC Pad Name Analog Ground Row Address Clock Interrupt External Clock Input Digital Supply Voltage Digital Supply Voltage Serial Clock Line Address 1 Serial Data Address Address 0 Digital Ground Digital Ground Analog Ground Non-inverting Microphone Input Inverting Microphone Input Non-inverting Analog Output Inverting Analog Output AGC/AutoMute Cap Speaker Negative Analog Ground Analog Ground Speaker Positive Analog Supply Voltage Analog Supply Voltage Analog Input Auxiliary Input Auxiliary Output X Axis 1882.40 1539.15 790.35 478.55 291.55 76.15 -198.45 -557.95 -815.25 -1366.45 -1668.35 -1839.95 -1945.05 -1739.25 -1506.75 -1245.05 -910.85 -623.55 -127.75 205.85 295.85 629.45 963.05 1053.05 1260.35 1525.95 1770.15 Y Axis 2820.65 2820.65 2820.65 2820.65 2820.65 2820.65 2820.65 2820.65 2820.65 2820.65 2820.65 2820.65 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 -2821.60 INT XCLK VCCD VCCD SCL A1 SDA A0 VSSD VSSD VSSA MIC+ MICANA OUT+ ANA OUTACAP SPVSSA VSSA SP+ VCCA VCCA ANA IN AUX IN AUX OUT - 81 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 12.6 ISD5104 DIE INFORMATION VSSD VSSD VCCD SDA SCL INT A1 VCCD XCLK A0 RAC VSSA ISD5104 Device Die Dimensions (include scribe line) X: 4230 m Y: 5046 m Die Thickness [3] 292.1 m 12.7 m Pad Opening Single pad: 90 x 90 m Double pad: 180 x 90 m ISD5104 VSSA MIC + MIC ANA OUT SP ANA OUT + ACAP VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. 2. 3. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or damage may occur. Double bond recommended, if treated as single doubled-pad. This figure reflects the current die thickness. Please contact Winbond as this thickness may change in the future. - 82 - ISD5100 - SERIES ISD5104 Pad Coordinates (with respect to die center in m) Pad VSSA RAC Pad Name Analog Ground Row Address Clock Interrupt External Clock Input Digital Supply Voltage Digital Supply Voltage Serial Clock Line Address 1 Serial Data Address Address 0 Digital Ground Digital Ground Analog Ground Non-inverting Microphone Input Inverting Microphone Input Non-inverting Analog Output Inverting Analog Output AGC/AutoMute Cap Speaker Negative Analog Ground Analog Ground Speaker Positive Analog Supply Voltage Analog Supply Voltage Analog Input Auxiliary Input Auxiliary Output X Axis 1882.4 1539.15 790.35 478.55 291.55 76.15 -198.45 -557.95 -815.25 -1366.45 -1839.95 -1668.35 -1945.05 -1739.25 -1506.75 -1245.05 -910.85 -623.55 -127.75 205.85 295.85 629.45 963.05 1053.05 1260.35 1525.95 1770.15 Y Axis 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 INT XCLK VCCD VCCD SCL A1 SDA A0 VSSD VSSD VSSA MIC+ MICANA OUT+ ANA OUTACAP SPVSSA VSSA SP+ VCCA VCCA ANA IN AUX IN AUX OUT - 83 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 12.7 ISD5102 DIE INFORMATION VSSD VSSD VCCD SDA SCL INT VCCD XCLK A1 A0 RAC VSSA ISD5102 Device Die Dimensions (include scribe line) X: 4230 m Y: 5046 m Die Thickness [3] 292.1 m 12.7 m Pad Opening Single pad: 90 x 90 m Double pad: 180 x 90 m ISD5102 VSSA MIC + MIC ANA OUT SP ANA OUT + ACAP VSSA [2] VCCA [2] SP + ANA IN AUX OUT AUX IN Notes 1. 2. 3. The backside of die is internally connected to Vss. It MUST NOT be connected to any other potential or damage may occur. Double bond recommended, if treated as single doubled-pad. This figure reflects the current die thickness. Please contact Winbond as this thickness may change in the future. - 84 - ISD5100 - SERIES ISD5102 Pad Coordinates (with respect to die center in m) Pad VSSA RAC Pad Name Analog Ground Row Address Clock Interrupt External Clock Input Digital Supply Voltage Digital Supply Voltage Serial Clock Line Address 1 Serial Data Address Address 0 Digital Ground Digital Ground Analog Ground Non-inverting Microphone Input Inverting Microphone Input Non-inverting Analog Output Inverting Analog Output AGC/AutoMute Cap Speaker Negative Analog Ground Analog Ground Speaker Positive Analog Supply Voltage Analog Supply Voltage Analog Input Auxiliary Input Auxiliary Output X Axis 1882.4 1539.15 790.35 478.55 291.55 76.15 -198.45 -557.95 -815.25 -1366.45 -1839.95 -1668.35 -1945.05 -1739.25 -1506.75 -1245.05 -910.85 -623.55 -127.75 205.85 295.85 629.45 963.05 1053.05 1260.35 1525.95 1770.15 Y Axis 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 2306.65 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 -2311.60 INT XCLK VCCD VCCD SCL A1 SDA A0 VSSD VSSD VSSA MIC+ MICANA OUT+ ANA OUTACAP SPVSSA VSSA SP+ VCCA VCCA ANA IN AUX IN AUX OUT - 85 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES 13. ORDERING INFORMATION Winbond Part Number Description I51 Product Family ISD5100-Series (1- to 16-minute durations) Duration: 16 = ISD5116 (8 to 16 min) 08 = ISD5108 (4 to 8 min) 04 = ISD5104 (2 to 4 min) 02 = ISD5102 (1 to 2 min) Special Temperature Field: Blank I = or = Commercial Packaged (0C to +70C) Commercial Die (0C to +50C) Industrial (-40C to +85C) When ordering ISD5100 Series devices, please refer to the following valid part numbers. TSOP SOIC DIE PDIP I5116E I5116EI I5116S I5116SI I5116X I5116P For the latest product information, access Winbond's worldwide website at http://www.winbond-usa.com } } Package Type: E S X P = = = = 28-Lead 8x13.4mm Plastic Package (TSOP) Type 1 Die 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) Thin Small Outline 28-Lead 300-Mil Plastic Small Outline Package (SOIC) Part Number I5108E I5108EI I5108S I5108SI I5108X N/A I5104E I5104EI I5104S I5104SI I5104X N/A I5102E I5102EI I5102S I5102SI I5102X N/A - 86 - ISD5100 - SERIES 14. VERSION HISTORY VERSION 0.1 0.2 DATE Mar 2003 Oct 2003 DESCRIPTION New data sheet for the ISD5100-Series Add I5102 and I5104 products Utilize TAD application in Functional Details Reserve Load Address feature for factory uses Simplify Playback mode AnaIn: add k for Ra & Rb AuxIn: add k for Ra & Rb, remove duplicate diagram, correct parameter names in gain setting table & fix typos Add application diagram Add PCB layout example for TSOP package I2C protocol: revise R/W bit =1 for reading status Packaging: revise unit to mil instead of inch for SOIC & PDIP Fix other typos - 87 - Publication Release Date: October, 2003 Revision 0.2 ISD5100 - SERIES The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental injury could occur. Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Winbond makes no representation or warranty that such applications shall be suitable for the use specified. ISD(R) and ChipCorder(R) are treademarks of Winbond Electronics Corporation. SuperFlash(R) is the trademark of Silicon Storage Technology, Inc. The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond. Information contained in this ISD(R) ChipCorder(R) data sheet supersedes all data for the ISD ChipCorder products published by ISD(R) prior to August, 1998. This data sheet and any future addendum to this data sheet is(are) the complete and controlling ISD(R) ChipCorder(R) product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. Copyright(c) 2003, Winbond Electronics Corporation. All rights reserved. ISD(R) is a registered trademark of Winbond. ChipCorder(R) is a treademark of Winbond. All other trademarks are properties of their respective owners. Headquarters No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 http://www.winbond-usa.com/ Winbond Electronics (Shanghai) Ltd. 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998 Taipei Office 9F, No. 480, Pueiguang Rd. Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. This product incorporates SuperFlash(R) technology licensed From SST. - 88 - |
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